Skills And Experience Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units. Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration. Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus). Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT. Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support. Language: English at a proficient level. French is a plus. Pay and benefits Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions. Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers). Relocation
