SoC and IP Design Engineer, Google Cloud

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques. Experience with design sign off and quality tools (e.g., Lint, CDC, etc.). Experience with SOC architecture. Experience in logic design. Preferred qualifications: Master's degree or PhD in Computer Science or a related technical field. Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate (DDR), Advanced Extensible Interface (AXI), or Advanced RISC Machines (ARM) processors family. Knowledge of high performance and low power design techniques. Knowledge of assertion-based formal verification. Excellent problem-solving and debugging skills.