Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience in RTL Design cycle from IP to SoC and from specification to production. 8 years of experience in Technical leadership. Experience in the following areas: RTL Design, Design Quality checks, Physical Design aspects of RTL coding, and Power. Preferred qualifications: Experience with synthesis techniques to improve Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques. Experience with Design For Test and its impact on Design and Physical Design. Experience with a scripting language like Python or Perl. Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, and ARM processors. Knowledge of SOC architecture and assertion-based formal verification. Knowledge of high performance and low power design techniques.
