Senior Digital Verification Engineer

BSc. in Electronic Engineering Minimum 5 years’ experience as a verification engineer, completing at least one chip development cycle. Developed verification environments Knowledge in verification methodologies and tools Knowledge of System Verilog UVM Scripting languages knowledge (perl, python) Methodological approach to the verification tasks planning and execution *Applicants are asked to take special care to avoid sharing, using, or disclosing any trade secrets or confidential information belonging to their current or former employers, from the time they apply and throughout the entire recruitment process.