Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. 8 years of experience in Automatic Test Pattern Generation (ATPG) methods. Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion. Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow. Experience in leading DFT activities throughout an ASIC development flow. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience in JTAG and iJTAG protocols and architectures. Experience in post-silicon test or product engineering. Experience in SoC cycles, silicon bring-up, and silicon debug activities. Knowledge of fault modeling techniques.
