What will your job look like: Hands-on physical design block owner, leading the process from RTL to GDS . Lead floorplan exploration in collaboration with Front-End and Architecture teams. STA: Partner with FE and floor planners to manage block and top-level constraints and perform 1st-level timing analysis. Synthesis: Conduct synthesis exploration and deliver final netlists, including scan insertion, UPF, and clean Lint/Spyglass checks. Place & Route: Drive the flow from synthesis netlist to final layout and signoff verification, with a focus on optimizing PPA (Power, Performance, and Area). All you need is: BSc or MSc in Computer Engineering or Electrical Engineering. 5+ years of experience in the Physical Design field Proficiency in scripting languages (Tcl, Python, Perl, or tcsh). A team player with excellent communication skills and a “can-do” attitude Experience in developing or maintaining implementation tools and design flows – an advantage Experience with high-speed interfaces (DDR/PCIE) - an advantage. Experience with advanced nodes (5nm and below) - an advantage.
