5+ years of experience in digital design Prefer previous experience in USB4, USB3, PCIe, and/or DisplayPort Experience in SoC front-end ASIC RTL digital logic design using Verilog or System Verilog Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug Good collaboration skills with strong written and verbal communication skills Familiarity with low-power design techniques such as clock- and power-gating is a plus Prefer familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB) Experience in front-end implementation tasks such as synthesis, timing, area/power analysis, linting, and logic equivalence checks Industry exposure to and knowledge of ASIC/FPGA design methodology including familiarity with AI/ML applications, relevant scripting languages (Python, Perl, TCL) BS.c / MS.c in EE/ CE
