What we need to see: B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience). At least 2 years of relevant experience Proficiency using Python, Perl, Tcl, Make scripting. Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes. Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required. Knowledge in process variation effect modelling and experience in design convergence taking into account variations. Successful track record of delivering designs to production is necessary. Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role. Ways to stand out from the crowd: Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus) Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an
