Lead an ASIC subsystem and understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks.
Define high-performance hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Implement designs in SystemVerilog.
Collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
4 years of experience architecting networking ASICs from specification to production.
Experience developing RTL for ASIC subsystems.
Experience in micro-architecture, design, verification, logic synthesis, and timing closure.
Preferred qualifications:
Experience architecting networking switches, end points, and hardware offloads.
Experience working with design networking like Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience working with software teams optimizing the hardware/software interface.
Experience in TCP, IP, Ethernet, PCIe, DRAM, Network on Chip (NoC) principles and protocols.
Experience in a procedural programming language (e.g., C++, Python, Go).
Understanding of packet classification, processing, queueing, scheduling, switching, routing, traffic conditioning, and telemetry.
