Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience. 8 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug). Experience developing full-chip/SoC tests using these environments/tools: ASM, C, C++, Perspec, Threadmill, OS, or drivers. Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., EP, HAPS, Protium). Experience with design debug tools (e.g., Verdi, Verisium). Experience with coding and scripting in C, C++, Perl, TCL, or Python. Preferred qualifications: Experience in embedded software and firmware (e.g., Linux drivers, firmware validation). Experience with associated electronic design automation (EDA) tools, automation, and flow enhancements. Experience with coding in Verilog/SystemVerilog for design. Understanding of SoC architecture and interfaces (e.g., CPU, DDR, PCIe, interconnect, Ethernet, etc.). Understanding of register transfer level (RTL) to emulation/field-programmable gate array (FPGA) flows including emulation test benches (e.g., transactors/accelerated verification intellectual properties (VIPs), hybrid, in-circuit emulation).
