What we need to see: B.Sc./M.Sc. in Electrical Engineering or Computer Engineering 8+ years of relevant experience in RTL/logic design, with multiple chips taken to tape-out Demonstrated technical leadership: leading a design area through implementation and tape-out, mentoring engineers, and coordinating across teams Expert hands-on RTL design skills in Verilog/SystemVerilog, with strong understanding of how RTL choices affect synthesis results, timing, area, and power Deep understanding of clocking and reset design: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing Proficiency with design quality tooling — lint, CDC/RDC, formal verification, synthesis, and static timing analysis (STA) — including the ability to interpret results and drive fixes back into the RTL Experience taking a design from architecture and micro-architecture specification through verification, physical implementation, and silicon bring-up Great teammate with strong communication skills across micro-architecture, DV, backend, DFT, and software teams Ways to stand out from the crowd: Prior hands-on experience with SOC-level clocking or reset logic on a taped-out chip Experience with PLL/clock generator integration and clock tree constraint development with backend teams Experience with high-speed networking, interconnect, or fabric designs Background with low-power design techniques (clock gating, DVFS, power domains, UPF) Experience building automation for RTL integration, chip assembly, or design quality flows At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiri
