Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience architecting networking ASICs from specification to production. Experience developing Register-Transfer Level (RTL) for ASIC subsystems. Experience with cross-functional engagement in micro-architecture, design, verification, logic synthesis, and timing closure. Preferred qualifications: Experience working with software teams optimizing the hardware/software interface. Experience architecting networking switches, end points, and hardware offloads. Experience working with design networking like: remote direct memory access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability. Experience in transmission control protocol (TCP), IP, ethernet, peripheral component interconnect express (PCIE) and dynamic random access memory (DRAM) including network on chip (NoC) principles and protocols (e.g., AXI, ACE, and CHI). Proficiency in procedural programming language (e.g., C++, Python, Go). Understanding of packet classification, processing, queuing, scheduling, switching, traffic conditioning, and telemetry.
