Apple
Seniority was normalized from the source posting. The posting date comes from source metadata.
Skill priority is derived from the source posting.
In this role you will be familiar with cutting edge power management techniques including power management ICs control schemes, Chip power state transitions, SoC boot process and HW security...
3+ years of experience in digital design (preferably in SoC) Familiar with advanced design practices (clock/voltage domain crossing, low power design and DFT) - Advantage Familiar with various chip development tools (e.g. lint, synthesis, STA) Familiar with verification methodologies Strong Verilog/System Verilog skills Experienced with scripting using common languages (e.g. Python, Perl, TCL) BS.c/ MS.c in EE/ CE
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