We are looking for a hands-on ETH SerDes Validation Engineer to lead and execute 112G
and next-generation 224G SerDes validation activities.
The role involves deep lab work with Keysight test equipment, automation development,
and direct execution of compliance and characterization tests according to industry standards.
This position is ideal for an engineer who combines strong signal-integrity fundamentals,
standards expertise, and automation-driven validation in high-speed silicon and system
environments.
Key Responsibilities
Perform end-to-end validation of 112G / 224G SerDes PHYs at silicon, package, and
system levels
Execute compliance, characterization, and stress tests for high-speed serial links
Operate And Configure Keysight High-speed Test Equipment, Including
BERTs, oscilloscopes, AWGs, jitter sources, channel emulators (variable ISI)
Develop And Maintain Automation Frameworks For SerDes Validation
Test setup control
Data collection
Result analysis and reporting
Python
Shell scripts under Ubuntu
SQL skills for data analysis
Execute And Analyze
Eye diagrams, jitter (RJ/DJ/TJ), BER, bathtub curves
CTLE/DFE behavior
TX FIR optimization
Channel loss and margin analysis
Debug Signal-integrity Issues Across
Silicon
Package
PCB
Connectors and cables
Work According To Industry Standards, Including
IEEE (112G / 224G PAM4)
Ethernet (802.3ck / 802.3db and beyond)
Collaborate Closely With
Design teams (SerDes / PHY)
SI/PI engineers
System and board design teams
Document test methodologies, results, and recommendations clearly
What We Offer
Work on cutting-edge 112G / 224G SerDes technologies
Direct impact on next-generation silicon and systems
Advanced lab environment with state-of-the-art Keysight equipment
Highly technical, expert-level team
Competitive Compensation And Benefits
Location in Kiryat Gat with access to major semiconductor programs
Requirements
5+ years of experience in high-speed SerDes validation or signal-integrity roles
Hands-on experience with 112G PAM4 SerDes validation
Strong working knowledge of Keysight validation platforms (BERTs, scopes,
automation APIs)
Proven ability to write automation scripts
Python
Shell scripts
SQL for Data Analysis
Deep Understanding Of
PAM4 signaling
Jitter decomposition
BER and margining techniques
Channel loss and equalization
Solid understanding of high-speed standards (Ethernet, IEEE, OIF)
Comfortable working independently in the lab and driving issues to closure
Experience with 224G SerDes validation or early silicon bring-up
Familiarity with Keysight N5991 / 8040 / 8160 / PNA / M8040A platforms
Experience Validating
112G / 224G Ethernet
Experience with compliance test specifications and interoperability testing
B.Sc. or M.Sc. in Electrical Engineering or equivalent
