3+ years of DFT experience, leading DFT efforts for complex chip designs We are counting on your expertise and knowledge about industrial standards and practices in DFT - including ATPG, JTAG, MBIST and trade-offs between test quality and test time You have experience developing DFT specifications and driving DFT architecture and methods for designs You are confident with Verilog and / or VHDL, and have experience with simulators and waveform debugging tools By now you are demonstrating proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-silicon You can debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG/1500 related issues You have experienced with STA constraints development and analysis for DFT modes and SDF simulations You love conducting experiments during silicon debug, gathering and analyzing data; and utilize scripting to support efficient handling of ATE data BS.c/ MS.c in EE/ CE
