Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. 4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools. Experience with industry-standard Automatic Test Pattern Generation (ATPG) methods, fault modeling, and scan coverage debug. Experience validating Memory Built-In Self-Test (MBIST) structures and Joint Test Action Group (JTAG)/ Test Access Port (TAP) controllers. Experience running structural verification, debugging testbenches, or simulation tracking utilizing simulators. Preferred qualifications: Master's degree in Electrical Engineering. Experience with the Tessent shell environment, specifically extracting Instrument Connectivity Language (ICL) networks. Familiarity with Silicon bring-up and validation on Automatic Test Equipment (ATE) testers, including debugging hardware execution patterns. Proficiency using Python or Tcl to manage complex Electronic Design Automation (EDA) design and sign-off flows.
