Senior ASIC Design Infrastructure & Methodologies engineer, MLA-MI - Annapurna Labs

Amazon

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Company: Amazon
Location: Tel Aviv
Office: HQ · 121 Menachem Begin Rd, Tel Aviv-Yafo, Israel
Field: Hardware Engineering
Role: Chip / ASIC Design Engineer
Type: Full Time
Level: Senior
Experience: 5+ yrs
Education: M.A
Posted: 15 Jul 2026

Seniority was normalized from the source posting. The posting date comes from source metadata.

Location

About Amazon

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Skills & technologies

AWS
Machine Learning
SOC

Description

Our Machine Learning Acceleration (MLA) team designs and develops the SOCs that power today's AI workloads across datacenters worldwide. As an ASIC Design Methodologies and Infrastructure Engineer,...

Requirements

7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience - 7+ years of digital design in communication systems experience - 7+ years of full-custom analog or RF layout experience - 7+ years of wireless communications systems and implementation experience - 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience - 7+ years of verification in communication systems experience - 5+ years of UVM, C, System C, and scripting experience - Master's degree or Ph.D. degree in Electrical Engineering or related field - Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs - Experience with modern ASIC/FPGA design and verification tools - Experience with SOC bring-up and post-silicon validation Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

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