Minimum qualifications: Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience. 8 years of Physical Design experience including 2 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling. Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures. Preferred qualifications: Proficiency with scripting languages commonly used in hardware automation (e.g., Tcl, Python, or Perl). Deep familiarity with ASIC physical design flows and methodologies, including synthesis, place and route (P&R), formal verification, and clock domain crossing (CDC). Solid fundamental knowledge of semiconductor device physics and transistor characteristics.
