Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog. Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power and design techniques. Experience in reasoning design and debug with Design Verification (DV). Preferred qualifications: Experience with a scripting language like Python or Perl. Experience with design sign-off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.). Knowledge of System on a chip (SOC) architecture and assertion-based formal verification. Knowledge of design techniques. Knowledge in one of these areas: Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Double Data Rate SDRAM (DDR), Advanced Extensible Interface (AXI), ARM processors.
