Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 4 years of experience with creating and using verification components and environments in standard verification methodology. Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs. Preferred qualifications: Master's degree or PhD in Electrical Engineering, or a related field. 3 years of experience creating and using verification components and environments in standard verification methodology. Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture. Experience with verification techniques, and the full verification life cycle. Experience with performance verification of ASICs and ASIC components. Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
