Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience. 8 years of experience in Design For Test from DFT architecture to post silicon production support. 4 years of experience with people management. Experience with DFT design and verification for multiple projects, DFT specification, definition, architecture, and insertion. Experience with DFT techniques and common industry tools, DFT and Physical Design flows, and DFT verification flow. Experience in leading DFT activities throughout the whole ASIC development flow. Preferred qualifications: Master's degree in Electrical Engineering or a related field. Experience in post-silicon Debug, test or product engineering. Experience in Joint Test Action Group (JTAG) and Internal JTAG (iJTAG) protocols and architectures. Experience in SoC cycles, silicon bring-up, and silicon debug activities. Knowledge of fault modeling techniques.
