Proven experience with PrimeTime for timing analysis, constraint development, and signoff Deep understanding of timing concepts: setup/hold analysis, clock domain crossing, multicycle paths, false paths, and timing exceptions Experience with advanced timing concepts: OCV, statistical timing analysis, margins and variation analysis Solid understanding of RTL-to-GDSII flow with focus on timing-critical stages Knowledge of power-aware timing analysis and low-power design methodologies Expert-level Python programming for automation, data analysis, and tool integration BS/MS in Electrical Engineering, Computer Engineering, or Computer Science Demonstrated track record of successful timing closure on complex designs Proficient in SQL with hands-on experience in MySQL and PostgreSQL for timing data management and analysis This role offers the opportunity to shape next-generation timing methodologies while working with cutting-edge technologies and talented engineering teams across HWTech.
