Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience. 8 years of experience in Design Verification with a focus on Mixed-Signal, PHY layers, DSP, Communication Systems, or Arithmetic Logic blocks. Experience with scripting in Python, Perl, or Makefile for automation. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field. Experience with Mixed-Signal Verification tools (e.g., Verilog-AMS, Real Number Modeling/RNM, or SystemVerilog-AMS). Experience leading verification through a full Silicon Life cycle (Plan to Tape-out). Experience with Performance Verification (throughput, latency, and power modeling). Experience in Formal Verification (JasperGold or similar) for complex state machines. Understanding of Adaptive Algorithms (FFE/DFE) and how to verify loop stability in a digital environment.
