Job Details Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a team developing cutting-edge HW for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads. We are continuously developing modern and effective working methods, including hands-on adoption of AI tools throughout the chip development flow. The environment is fast-paced and intellectually stimulating. Your Mission: Integrate hardware security IP into the SoC/die and define the HW security architecture protecting a large-scale data center's compute, network, and control infrastructure. Responsibilities Integrate third-party and internal HW security IP (Root of Trust, crypto engines, HSMs, TRNG, key vaults) into the die; write and own the RTL/integration code wiring these units into the SoC. Author RTL for security units, glue logic, fuse/OTP interfaces, and bus/fabric (AXI/AHB/NoC) connections; manage clock/reset/power domains and CDC. Develop integration test benches, run lint/CDC/synthesis-readiness checks, and support DV/verification of the embedded security IP. Architect platform Root of Trust, secure boot, attestation, and confidential computing (TDX/SGX/SEV-equivalent) across the server fleet. Threat-model the full stack (silicon, firmware, BMC, supply chain) and define HW mitigations against physical and side-channel attacks. Drive secure key management, debug-lockdown, fuse provisioning, and crypto offload for tenant isolation at scale. Collaborate closely with architecture, design verification, physical design, firmware, and platform teams throughout the development cycle. Qualifications B.Sc., M.Sc., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field. 5+ years of experience in RTL development, SoC design, or hardware security integration. Proficient in Verilog/SystemVerilog RTL, IP integration, bus protocols (AXI/AHB/NoC); lint, CDC, synthesis, DV flows.
