Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience architecting networking ASICs from specification to production or equivalent experience. 4 years of experience in technical leadership. Experience developing RTL for ASIC subsystems. Experience in micro-architecture, design, verification, logic synthesis, and timing closure. Experience in Micro-Architecture, RTL Design, Verification, Design Quality checks, Physical Design aspects of RTL coding, and Power. Preferred qualifications: Experience architecting networking switches, end points, and hardware offloads. Experience working with design networking: RDMA or packet processing and system design principles for low latency, high throughput, security, and reliability. Experience working with software teams optimizing the hardware/software interface. Familiarity with Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI). Proficiency in a procedural programming language (e.g., C++, Python, Go). Knowledge of TCP, IP, Ethernet, PCIE and DRAM.
