Design Verification Engineer

5+ years of experience in SoC or IP verification Advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows and broad system view Expected to have a deep understanding and shown experience in advanced verification processes, including coverage driven and formal methods Extensive experience with SystemVerilog and UVM Experience with verification infrastructure development Knowledge of storage IPs and control oriented design - an advantage Knowledge of formal, hardware acceleration – an advantage Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL B.Sc / M.Sc in Electrical or Computer Engineering