BS.c or MS.c in Electrical Engineering 7+ years of Physical Design experience on high-performance, low-power SOC Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floorplaning, and Place & Route Experience in developing and implementing Powergrid and Clock specifications Solid Understanding of all aspects of Physical construction, Integration, and Physical Verification Working Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able to work with the logic design team on timing fixes Power user of industry-standard Physical Design & Synthesis tools Solid Understanding of scripting languages such as Perl/Tcl Working knowledge of Extraction and STA methodology and tools Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at the chip/block level Strong communication skills, as the candidate will interface with a lot of different groups within the company Ability to work well in a team and be productive under a tight schedule
