Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience in RTL Design cycle IP and SoC. 8 years of experience in team management. Experience with design methodologies, structural checks, and power estimation. Preferred qualifications: Experience with synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques. Experience with a scripting language like Python or Perl. Experience with design for test and its impact on design and physical design. Knowledge of IP and SOC architecture. Knowledge of physical design techniques: SDC, Synthesis, EMIR, etc.
