Apple
Seniority was normalized from the source posting. The posting date comes from source metadata.
Skill priority is derived from the source posting.
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development,...
5+ years of work experience Knowledge of the ASIC design timing closure flow and methodology At least 2+ years of experience in writing ASIC timing constraints and timing closure Expertise in STA tools (Primetime) and flow Knowledge of Timing corners/ modes Hands on experience in Timing / SDC constraints generation and management, proficient in scripting languages (Tcl and Perl) Familiarity with synthesis, DFT and backend related methodology and tools B.Sc / M.Sc in Electrical or Computer Engineering
Listing aggregated by Goozali Jobs. Apply on the employer's site.
