Digital Verification Engineer

BSc in Electrical/Electronic Engineering or Computer Engineering. 3+ years as a Verification Engineer, including at least one full chip or IP development cycle. High ambition, passion for solving complex hardware challenges, and a proven motivation to learn and adapt to new technologies. Hands-on expertise in SystemVerilog and UVM, including building environments from scratch. Proficiency with standard verification tools, simulators, and regression managers. Strong scripting skills in Python/Perl and experience with Linux/Unix environments. Methodical approach to verification planning, execution, and tracking. Experience using AI tools to accelerate verification, improve test generation, or optimize workflows.