6+ years of Logic Design experience. Advanced knowledge of ASIC RTL design methodologies Advanced knowledge of standard ASIC verification flows including simulation and testbench development. Working knowledge of frontend tools (Synthesis, STA, etc’) Excellent knowledge of System Verilog, Verilog. Good knowledge of C / C++. Experience with either Python/Perl/Tcl scripts. Knowledge of industry standard interfaces and experience with multiple frontend simulators/debuggers. A teammate with excellent interpersonal skills and the desire to pursue diverse challenges. BS.c / MS.c EE or BS.c / MS.c CE. Hands-on experience with signal processing design. Knowledge of formal verification & methodologies.
