BSc in Electrical Engineering 8+ years of industry experience, including verification team leadership Strong DV background with testbench development Experience with low-power verification, formal, FW verification, or emulation is a plus Proficiency in SystemVerilog and UVM Ability to lead teams to high-quality outcomes Define verification architecture and lead for execution Own verification methodologies, standards, and best practices across the team Drive improvements in verification flows and methodologies Collaborate closely with design teams on specifications, architecture, test plans, and testbench development MSc in Electrical Engineering
