Educatio: Minimum requirement of BS + 8 years of relevant industry experience Key qualifications Requires experience in Silicon chip design flows, including place-and-route (PnR) implementation flows Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/MFILL is required. Rule coding in PERC is a plus Tapeout support and SoC chip-level PDV debug experience in various technology nodes is desirable Hands-on experience with PnR tools and physical implementation flow is preferred Knowledge/scripting in programming languages such as Perl, Python, Tcl, Shell, Makefile and/or C++ Deep understanding of Silicon technology and experience with flow development in advanced nodes Knowledge of parasitic extraction and Virtuoso SKILL coding is a plus
