Staff RTL IP/Component Design Engineer, Google Cloud

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Experience in ASIC development with Verilog/SystemVerilog, VHDL or Chisel. Experience with System on a Chip (SoC) development cycles. Preferred qualifications: Proficiency with a scripting language (e.g., Python or Perl). Knowledge of high performance and low power design techniques. Knowledge of assertion-based formal verification. Knowledge of FPGA and emulation platforms. Knowledge of SOC architecture. Knowledge in one of these areas: arithmetic units, bus architectures, processor design, accelerators or memory hierarchies.