Job Details:
Job Description:
As part of Intel's Core Engineering Group, we develop Intel's main and most valuable and complex IP: the Intel Performance Core. The Core is the central component of many Intel products, including desktops, notebooks, servers, cloud CPUs, and emerging AI platforms.
Our Core technology powers hundreds of millions of products every year and drives innovations across cloud computing, AI, networking, communications, and consumer markets.
The team is responsible for developing and managing critical mechanisms at the heart of Intel's next-generation Performance Core architecture. Our work has a direct impact on performance, power efficiency, scalability, and product competitiveness across Intel's CPU portfolio.
About the Job
We are looking for an experienced Logic RTL Design Engineer to join the Out-of-Order team.
In this role:
you will define micro-architecture, develop RTL, and drive the implementation of complex allocation and resource management mechanisms in Intel's high-performance CPU cores.
You will own features from architecture exploration through RTL development, validation support, debug, and tape-in readiness.
You will lead significant design efforts, drive micro-architectural tradeoff discussions, and collaborate closely with architecture, verification, physical design, power-performance, and post-silicon teams.
This is a unique opportunity to influence core technologies that directly impact CPU performance, power efficiency, and scalability while contributing to future generations of Intel Core products.
Qualifications:
B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
At least 5 years of experience in RTL logic design and development using SystemVerilog.
Strong understanding of computer architecture, micro-architecture, and digital design principles.
Experience defining and implementing complex micro-architectural features.
Strong debugging and problem-solving skills.
Ability to independently drive features from definition through implementation and validation.
Excellent communication and teamwork skills.
Experience collaborating with architecture, validation, design, and post-silicon teams.
Nice to Have
Experience with design partitioning and micro-architectural tradeoff analysis.
Experience developing functional validation and coverage plans together with verification teams.
Experience working on high-performance CPU or cache/memory subsystem designs.
Experience with timing closure, power optimization, and performance analysis.
Knowledge of power-aware RTL coding methodologies and power debugging techniques.
Familiarity with advanced design methodologies, scripting, and automation.
Experience working with geographically distributed and cross-functional engineering teams
Job Type:
Experienced Hire
Shift:
Shift 1 (Israel)
Primary Location:
Israel, Haifa
Additional Locations:
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*
