Define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, VHDL), function/performance simulation debug, and Lint/CDC/FV/UPF checks.
Participate in synthesis, timing/power, and FPGA/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking ASICs from specification to production.
8 years of experience in technical leadership.
Experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
Experience developing RTL for ASIC subsystems.
Preferred qualifications:
Experience working with design networking like: Remote Direct Memory Access (RDMA) or packet processing and system design principles for low latency, high throughput, security, and reliability.
Experience in TCP, IP, Ethernet, PCIE and DRAM including Network on Chip (NoC) principles and protocols (AXI, ACE, and CHI).
Experience architecting networking switches, end points, and hardware offloads.
Understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.
