Must-Haves 3+ years of experience in FPGA design and digital system development. Strong proficiency in Verilog/SystemVerilog RTL design. Hands-on experience with Xilinx FPGA families (UltraScale+, Zynq, or Versal). Experience implementing and debugging high-speed interfaces (PCIe, Ethernet, JESD, or similar). Solid understanding of FPGA development flows, including synthesis, place & route, and timing closure. Experience with lab debugging tools (e.g., ILA/ChipScope, oscilloscopes, logic analyzers). Experience with simulation and verification methodologies (RTL and gate-level). Strong problem-solving skills and attention to detail. B.Sc. or higher in Electrical Engineering, Computer Engineering, or equivalent. Strong communication skills and ability to collaborate across teams.
