FE integration & STA IP Lead- Advanced Technologies Group

Bsc/Msc in Electrical Engineering 5+ years of experience in the field At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure Expertise in STA tools (Primetime) and flow generation Knowledge of the ASIC design timing closure flow and methodology Understanding of timing corners/modes Familiarity with process variations and signal integrity-related issues Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl) Knowledge of synthesis, DFT, and backend-related methodologies and tools Strong communication skills are required, as you will interact with various groups