We are looking for an excellent design engineer to join our team and build QM's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface
Requirements:
BSc in electrical/computer engineering or relevant military background
At least 4 years of experience
Proven track record in RTL coding with System Verilog
Experience with System Verilog
VCS, Vivado - Advantage
Requirements
Preferred Skills
