About the Business Unit:
Ceva develops state-of-the-art DSPs, AI processors, and hardware-accelerator IP for AI, vision, wireless, and base-station applications. Our VLSI organization transforms advanced architecture into production-ready silicon IP across leading technology nodes.
About the Role:
We are looking for an experienced physical-design leader who wants to remain close to technology while leading an accomplished engineering team.
You will lead a team of experienced backend engineers across Israel and India and own delivery across multiple projects in parallel.
This hands-on leadership role combines approximately 50% technical work and 50% team management, with end-to-end responsibility for turning complex RTL into tape out-ready GDSII.
Responsibilities:
Own and drive the complete RTL-to-GDSII flow, including synthesis, implementation, timing closure, physical verification, signoff, and tape out-ready IP delivery.
Lead, mentor, and develop a distributed team of experienced engineers while setting priorities and ensuring predictable, high-quality execution.
Provide hands-on leadership in flow development, advanced technology-node bring-up, integration, automation, and complex design closure.
Partner with architecture, frontend, verification, and other stakeholders to remove technical roadblocks and continuously improve backend methodologies.
The role includes working closely with customers and supporting backend convergence of the IP.
Requirements
B.Sc. or M.Sc. in Electrical Engineering
At least 10 years of hands-on experience in VLSI backend or physical design
Proven managerial or team-lead experience and the ability to guide a highly experienced engineering team.
Deep knowledge of synthesis, place and route (P&R), static timing analysis (STA), physical verification, and signoff flows.
Proven ownership of complete RTL-to-GDSII execution for complex designs, including advanced process technologies of 7nm and below.
Strong TCL and Python scripting skills, together with excellent troubleshooting, communication, prioritization, and collaboration capabilities.
Advantages:
Top-level integration experience for a multi-partition SoC.
Strong understanding of RTL design using Verilog or SystemVerilog.
Experience developing physical-design flows, infrastructure, or advanced-node methodologies.
