What we need to see: B.Sc./M.Sc. in Electrical Engineering or Computer Engineering 3+ years of relevant experience in RTL/logic design Solid hands-on RTL design skills in Verilog/SystemVerilog, with a good understanding of synthesis, timing, and how RTL choices affect the physical implementation Experience taking a design from micro-architecture specification through verification and physical implementation Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis) Great teammate with strong communication skills across micro-architecture, DV, and backend teams Ways to stand out from the crowd: Passion for quality, and a track record of clean deliveries to physical design, DV, emulation, firmware, and other downstream customers Prior ownership of SOC-level clocking or reset architecture on a taped-out chip Experience with PLL/clock generator integration and clock tree constraint development with backend teams At NVIDIA, you will be immersed in a diverse and encouraging environment where everyone is encouraged to do their best work. Join us and see how you can make a lasting impact on the world. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law
