Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Experience with design sign-off and quality tools (e.g., Lint , CDC , etc.). Experience with SoC or IP architecture. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, Field-programmable Gate Array (FPGA) and emulation platforms, and SoC architecture. Knowledge in one of the following areas such as Double Data Rate (DDR)/Low Power Double Data Rate (LPDDR), High-bandwidth memory (HBM). Excellent problem-solving and debugging skills.
