Define the long-term firmware roadmap and hardware-software partitioning for physical-layer interfaces, determining the optimal balance between hardware-fixed logic and programmable firmware.
Architect advanced "in-situ" monitoring systems and firmware-driven diagnostics to track physical-layer link health, Bit Error Rate (BER) trends, and channel quality across millions of ports in real-time.
Design, model, and implement bare-metal or RTOS firmware to control high-speed transceivers, managing real-time adaptive loops, clock and data recovery (CDR), and physical-layer calibration.
Partner with TPU Systems, Networking Software, and High-Performance Computing (HPC) teams to ensure silicon firmware integrates seamlessly with global cluster management and collective communication frameworks.
Identify and de-risk hardware-software interface bottlenecks (e.g., register maps, driver latencies, and boot-up sequencing) that impact Google's AI infrastructure.
Minimum qualifications:
Bachelor’s degree in Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
10 years of industry experience in embedded systems/firmware, communication systems engineering, or digital signal processing (DSP) development.
Experience developing embedded software (C/C++) for high-speed physical-layer interfaces (PHY), digital transceivers, or communication subsystems.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
Expertise in Forward Error Correction (FEC) algorithms and advanced modulation schemes.
Track record defining firmware framework specifications, register maps, and Silicon Life-cycle Management telemetry for high-volume networking or AI silicon.
Background in wireless communications with deep domain knowledge of channel modeling, noise mitigation, and digital transceiver architectures.
