We are seeking an IC Product Engineer to drive silicon validation, yield optimization, and product maturity from initial tape-out through high-volume manufacturing.
In this role, you will act as the technical bridge between Design, Test, Quality, and Foundry and OSAT partners. You’ll leverage advanced statistical analysis to convert complex ATE data into actionable yield and quality improvements.ng requisitions 'from scratch'.
Duties And Responsibilities
Yield Learning & Optimization: Drive wafer-level and final test yield enhancement programs. Identify root causes of yield drop, parametric shifts, and low-yield excursions across multiple manufacturing lots.
Data Analysis & Reporting: Use statistical tools to analyze large-scale ATE data, perform correlation analysis, establish guard bands, and track yield metrics across OSATs and foundries.
Silicon Validation & Characterization: Partner with Design and Test teams to define characterization plans, perform shmoo plot analysis, evaluate thermal/voltage margins, and establish production test limits.
Production Support: Support manufacturing, review yield baseline shifts, drive continuous improvement programs, and manage product hold disposition rules.
Quality & Reliability: work on Failure Analysis and Reliability investigating customer returns (RMA), qualifying new packages or process nodes, and supporting qualification tasks (i.e. ESD/LU, HTOL etc).
Requirements
Skills and qualifications:
Test Engineering Background: Direct experience with ATE platform hardware and test program development (e.g., Teradyne Ultraflex) a big advantage
Familiarity and experience working with foundry & OSAT : Familiarity with fab processes, WAT data, and packaging assembly flows.
Automation- Proficiency in scripting for data extraction and automation (i.e. Python, PERL).
Minimum 5+ years of experience in Semiconductor Product Engineering (post-silicon bring-up to high-volume production).
Deep understanding of statistical process control, baseline drift detection, capability metrics (CPK ), and correlation methodologies (wafer vs. package test).
BSEE/MSEE, Computer Engineering, Microelectronics.
