What will your job look like: You'll be responsible for the architecture of DFT solutions across the SOC (MBIST, SCAN, ATPG, LBIST and more). Develop all the necessary RTL for the different modules. Verify and Validate your design in GLS. Develop ATPG to the highest requirements of Functional Safety (ISO26262). Debug and analyze coverage and yield loss. Support production activities and Si debug. All you need is: BSc or MSc in Electrical and Electronics Engineering. Proven Experience in either SCAN or MBIST tools and flows. At least 2 years of DFT experience in both SCAN/MBIST. At least 2 years of experience in the ASIC/SoC industry. Excellent communication skills and team spirit.
