Design Verification Engineer

+6 years of experience in SoC Verification You will need to have advanced knowledge of SoC architecture/design, in-depth knowledge of verification flows, and a broad system view Expected to have a deep understanding and shown experience in advanced verification processes, including dynamic, coverage-based, and formal methods Extensive experience with System Verilog or UVM Experience with verification infrastructure development Scripting and programming experience using several of the following: Perl, Python, Verilog, SystemVerilog, C, C++, and TCL – an advantage B.Sc / M.Sc in Electrical or Computer Engineering