Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IP’s, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.
Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience in RTL design cycle from IP to SoC, from specification to production.
8 years of experience in execution teams management.
Experience in the following areas: RTL design, design quality checks, physical design aspects of RTL coding, and power.
Preferred qualifications:
Experience with synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
Experience with a scripting language like Python or Perl.
Experience with design for test and its impact on design and physical design.
Knowledge of one of the following areas: PCIe, UCIe, DDR, AXI, CHI, Fabrics, ARM processors family.
Knowledge of SoC architecture and assertion-based formal verification.
Knowledge of high performance and low power design techniques.
