Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 4 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools. Experience with ASIC DFT synthesis, simulation, and verification flow. Experience in DFT specification, definition, architecture, and insertion. Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues). Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)). Experience in SoC cycles, silicon bringup, and silicon debug activities. Experience in fault modeling.
