Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 8 years of experience working on main interconnects, Direct Memory Access (DMA), controllers, and power management. Experience capturing design specification in a temporal assertion language such as SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. Experience working with one or more formal verification tools, such as JasperGold, VC Formal, Questa Formal, or 360-DV. Understanding of formal verification algorithms. Proficiency with scripting languages, such as Python.
